The present invention relates to semiconductor memories and more particularly to control and timing logic circuits for supplying refresh pulses in a manner which does not interfere with the normal operation of the memory system. Dynamic memories are presently employed in data processing systems which employ charge-storing elements for storing data therein. This type of semiconductor memory has the advantage of high-speed access operation but has the disadvantage of having the charge leaking from the storing elements, thereby requiring that the charge be regenerated or refreshed so as not to lose the data represented by the charge level. In order to overcome this problem, prior art arrangements have been devised to provide refresh operations which are synchronized with the access operation of the memory systems so as to appear transparent to the central processor. But where there are other devices on line with the memory system which devices may interrupt the normal processing operation or where there is a power down of the memory system, it is necessary to insure that the data stored in the memory is not lost. It is therefore an object of this invention to provide an improved digital semiconductor memory system. It is a further object of the invention to provide a semiconductor memory system which includes circuit means for controlling the accessing and refreshing of the memory system while providing a minimum of interference between the access and refresh operations. It is another object of this invention to provide a memory system having improved access and refresh contention circuits which are composed of a relatively low number of digital elements and therefore, low in cost.